1. Technical Field
The present invention relates to an output driver, and more particularly, to an output driver for outputting a data strobe signal.
2. Related Art
A data strobe signal output driver is used to output a data strobe signal (DQS) in a semiconductor memory apparatus. In the semiconductor memory apparatus, the data strobe signal (DQS) is a signal which is outputted to transfer the timing value of data when outputting the data through a data pad.
Since the data strobe signal (DQS) serves as a signal for transferring the timing value of the outputted data as described above, the data strobe signal (DQS) plays an important role in high speed operations of a semiconductor memory apparatus and in applications that use the semiconductor memory apparatus. Therefore, timing-related specifications of the data strobe signal (DQS) including slew rate, Vox, duty, etc. are determined, and the semiconductor memory apparatus is provided with a data strobe signal output driver which can output the data strobe signal (DQS) conforming to the specification.
FIG. 1 is a block diagram illustrating a conventional data strobe signal output driver.
The conventional data strobe signal output driver includes a trigger block 10, a first predriver block 21, a second predriver block 22, and a main driver block 30.
The trigger block 10 receives a first signal rsig, a second signal fsig, a first clock rclk, a second clock fclk, a driver off signal drv_off, a termination enable signal odt_on and a preamble signal pream, and outputs a first predrive signal pup and a second predrive signal dpn.
The first predriver block 21 receives the first predrive signal pup and outputs a first main drive signal up based thereon.
The second predriver block 22 receives the second predrive signal pdn and outputs a second main drive signal dn based thereon.
The main driver block 30 outputs a data strobe signal DQS by charging an output node no according to the first main drive signal up or discharging the output node no according to the second main drive signal dn. The main driver block 30 is generally configured to include a pull-up driver unit (not shown) for charging the output node no and a pull-down driver unit (not shown) for discharging the output node no. The pull-up driver unit is comprised of a PMOS transistor which receives the first main drive signal up, and the pull-down driver unit is comprised of an NMOS transistor which receives the second main drive signal dn.
The data strobe signal output driver generates the first and second predrive signals pup and pdn through the trigger block 10, generates the first and second main drive signals up and dn through the first and second predriver blocks 21 and 22, and outputs the data strobe signal DQS through the main driver block 30. Also, the data strobe signal output driver generates a preamble pulse according to the preamble signal pream before the activation timing of the data strobe signal DQS.
In general, when a semiconductor memory apparatus outputs data, the first and second main drive signals up and dn should have the same value so that the main driver block 30 can generate the data strobe signal DQS by charging or discharging the output node no. Signals for controlling charge or discharge of the output node no by the main driver block 30 are generated by the first and second predriver blocks 21, 22. More specifically, the first main drive signal up and the second main drive signal dn are respectively generated by the first predriver block 21 and the second predriver block 22. Thus, the output waveform of the data strobe signal DQS is determined depending upon how precisely the first main drive signal up and the second main drive signal dn are matched to each other at the same timing.
FIG. 2 is a circuit diagram illustrating the first predriver block 21 and the second predriver block 22 shown in FIG. 1.
The first predriver block 21 includes a first PMOS transistor P1 and a first NMOS transistor N1, which each receive the first predrive signal pup via its respective gate terminal, and a first slew rate resistor Rs1. The second predriver block 22 has the same configuration as the first predriver block 21 and includes a second PMOS transistor P2 and a second NMOS transistor N2, which each receive the second predrive signal pdn via its gate terminal, and a second slew rate resistor Rs2. In the first predriver block 21, the first PMOS transistor P1 and the first NMOS transistor N1 are turned on or off based on the first predrive signal pup, the slew rate of the first predrive signal pup is controlled by the first slew rate resistor Rs1, and the first main drive signal up is output in response thereto. The second predriver block 22 has the same configuration and operates in the same manner as the first predriver block 21.
As described above, the first predriver block 21 and the second predriver block 22 each include a PMOS transistor, a NMOS transistor and a slew rate resistor as shown in FIG. 2. Therefore, because the first main drive signal up and the second main drive signal dn are signals which are respectively output from the first predriver block 21 and the second predriver block 22 as different component parts, the first main drive signal up and the second main drive signal dn may have different timings due to changes in PVT (process, operating voltage and temperature) and a difference between a designed value and a realized value. As such, since the output waveform of the data strobe signal DQS is dependent on how precisely the first main drive signal up and the second main drive signal dn are matched to each, providing the first main drive signal up and the second main drive signal dn via different predriver blocks can serve as a disadvantage to the timing specification of the data strobe signal DQS including slew rate, Vox, duty, etc. As a semiconductor memory apparatus operates at a gradually increasing speed, such a disadvantage may be serious since the timing specification of the data strobe signal DQS is established to conform to the high speed operation.